The present invention is generally directed to a method for the formation of gate electrodes in VLSI transistor devices, particularly metal oxide semiconductor (MOS) devices. More particularly, the present invention is directed to the construction of symmetrical and non-symmetrical submicron gate, self-aligned inlay transistors. Even more particularly, the present invention is directed to an edge defined method for formation of gate electrodes and other narrow width, conductive electrical circuit patterns on integrated circuit chips. The present invention is also directed to an inlay MOS transistor structure.
In the fabrication of integrated circuit chips, one of the major design goals of electrical circuit technology over the last two decades has been the reduction in size of electrical circuit components, particularly components employed in digital circuit devices including memories, processor chips, and the like. One of the requirements for such miniature devices is the fabrication of electrical circuit conductive patterns of extremely narrow width. As device size has shrunk, engineers and physicists involved in device fabrication have found limitations in optical resolution and mask alignment to be critical process aspects which tend to limit the extent to which device size can be decreased.
One of the devices that is particularly amenable to incorporation into VLSI circuits is the metal-oxide-semiconductor (MOS) field effect transistor (FET). High performance MOSFETs in particular often employ a symmetrical structure in which there is present a lightly doped source and drain region adjacent to the gate so as to reduce the effects of high field strengths in the gate region. These high field strengths are a direct consequence of the small distances between device structures. However, it is also desirable to form non-symmetrical high performance FETs on the same integrated circuit chip. The high performance FET is desirable because it has a low impedance source to offset parasitic series impedance effects caused by lightly doped source or drain regions adjacent to the gate. However, symmetrical devices are also desirable for pass gate circuit elements. Accordingly, in any method which attempts to further decrease circuit line widths, it is desirable to be able to construct both symmetrical and non-symmetrical FETs on the same circuit chip.
One of the limiting factors in the reduction of FET device size is the inherent width of the gate electrode. In conventional processing the gate electrode comprises a metal layer or a layer of doped polysilicon which is initially deposited over the whole substrate, wafer or chip. This material is then selectively etched using a "gate" mask pattern to provide the desired conductive pattern extending over the active area of an FET device with the source and drain region lying in the active area on either side of the gate electrode. Such devices are limited by the ability of processes to make the gate width small. Accordingly, it is desired to be able to shrink electronic circuit device sizes by providing a method for fabricating conductive patterns of very narrow widths, typically less than 0.5 microns. It is also desirable to be able to employ device fabrication processes which are not limited by optical or lithographic resolution. Moreover, it is desirable to be able to employ fabrication processes in which mask alignment is not critical. Lastly, but not limited hereto, it is desirable to be able to employ fabrication processes in which both symmetrical and non-symmetrical FET devices may be fabricated on the same chip without incurring the cost of increased process complexity and concomitant process yields. The problem of gate electrode definition is an important one in VLSI processing. If the gate is made too thin, problems of ion implantation masking effectiveness begin to evidence themselves and thus limit reduction in device size and deleteriously impact device characteristics. Thus, it is seen that it is desirable to have and to easily fabricate devices with a high gate height to width ratio, that is, with a high aspect ratio.
Another problem that exists in MOSFET devices is the inherent parasitic capacitance which exists as a result of large source and drain contact areas. Such capacitances limit device speed.